1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a multilevel interconnections in a semiconductor integrated circuit device.
2. Description of the Related Art
The importance of a fabrication technology of multilevel interconnections for a semiconductor integrated circuit device, particularly VLSI device is on the increase because the quality of the multilevel interconnections defines a degree of integration or a packing density, device performance, yield and reliability. Possible improvements in the high integration, the device performance, the yield and the reliability depends upon the fabrication method of the multilevel interconnections in the semiconductor integrated circuit.
A typical and conventional fabrication method of multilevel interconnections in a semiconductor integrated circuit device is disclosed in 1989, IEEE International Electron Devices Meeting Technical Digest pp. 669-672. The fabrication method of multilevel interconnections will be described with reference to FIGS. 1A and 1B.
With reference to FIG. 1A, a semiconductor substrate 1 which has been formed with diffusion layers is prepared. A first silicon oxide film 2 is formed on the semiconductor substrate 1. A layer made of aluminum is deposited on the first silicon oxide film 2 for a subsequent receipt of patterning to form aluminum wiring lines 3 on the first silicon oxide film. An atmospheric pressure chemical vapor deposition which uses tetraethoxysilane (TEOS) and an oxygen including ozone as source gases is accomplished thereby a second silicon oxide film 5 is deposited on the second silicon oxide film 2 so as to cover the aluminum wiring lines 3.
With reference to FIG. 1B, after an alignment of a photo-resist which has been patterned, the first and second oxide films 2 and 5 are subjected to a selective etching which uses the photo-resist pattern. As a result, a through hole is formed both in the first and second oxide films 2 and 5 so that a part of a surface of the semiconductor substrate 1 is exposed through its through hole. Another through hole is concurrently formed in the second silicon oxide film only but directly over the aluminum wiring line 3 so that a part of the aluminum wiring line 3 is exposed through its through hole. A layer made of aluminum is deposited on an entire surface of the device so that the through holes are filled with the aluminum layer. The deposited aluminum layer receives such a patterning as to make the aluminum layer remain only within and in the vicinity of through holes. This results in a formation of aluminum wiring lines comprising the remaining aluminum layers which are in contact with the surface of the semiconductor substrate 1 and the aluminum wiring lines 3 underlying the second silicon oxide film 5 respectively.
Actually, the above processes will be repeated several times for the formation of the multilevel interconnections, although illustrations thereof are omitted. The second silicon oxide film 5, thus, serves as an interlayer insulator.
The quality of the multilevel interconnections in the semiconductor integrated circuit device will be investigated with reference to FIGS. 2A and 2B.
As described above, the second silicon oxide film 5 was formed by the atmospheric pressure silicon chemical vapor deposition which uses tetraethoxysilane and the oxygen including ozone as source gases. As illustrated in FIG. 2A, the second silicon oxide film 5 serving as the interlayer insulator has an excellent flatness but only at a part over the aluminum wiring lines 3. The second silicon oxide film except for the part over the aluminum wiring lines 3 has a surface having a poor leveling quality. Namely, an extremely inferior leveling grade appears at the surface of the second silicon oxide film except for the part over the aluminum wiring lines 3. The second silicon oxide film except for the part over the aluminum wiring lines 3 includes many bubbles or voids 5a. Such appearances of both the bubbles or voids 5a in the second oxide film 5 and the extremely inferior leveling quality of that surface are increasingly considerable when the flow rate of ozone and the thickness of the second oxide film are on the increase.
Such undesirable phenomenon of the extremely inferior leveling quality and the many bubbles or voids 5a also appears when the second silicon oxide film 5 is deposited by the atmospheric pressure chemical vapor deposition after a silicon oxide film is deposited by a plasma chemical vapor deposition.
When the through hole is formed in the second silicon oxide film 5 including the bubbles or voids 5a, the through hole also has a side wall having a poor leveling quality which is deemed to be caused by the bubbles or voids 5a. It appears that such side wall having a poor leveling quality of the through hole causes a disconnection 8b of the aluminum wiring line 8 within the through hole. Further, it appears that after the etching process for the aluminum layer, the aluminum layer remains not only within and in the vicinity of the through holes but also on the surface of the second silicon oxide film 5. The remaining aluminum layer on the surface of the second silicon oxide film 5 causes a short of the aluminum wiring lines 8.
Consequently, the use of the atmospheric pressure chemical vapor deposition for formation of the second silicon oxide film results in an inferior leveling of the surface of the second silicon oxide film 5 and the existence of the many bubbles or voids in the second silicon oxide film 5. These cause the disconnection and the short of the aluminum wiring lines 8 thereby resulting in a considerable inferiority of the device performance, yield and reliability of the semiconductor integrated circuit including such silicon oxide film 5 being formed by the conventional atmospheric pressure chemical vapor deposition method.
In replacement of such conventional fabrication process, it is therefore required to develop a novel fabrication method of the multilevel interconnections, which makes the interlayer insulator free from both the inferior leveling of the surface of the interlayer insulator and the appearances of the bubbles or voids in the interlayer insulator.